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| CY7C1062DV33 16-Mbit (512K X 32) Static RAM Features Functional Description The CY7C1062DV33 is a high performance CMOS Static RAM organized as 524,288 words by 32 bits. To write to the device, take Chip Enables (CE1, CE2, and CE3 LOW) and Write Enable (WE) input LOW. If Byte Enable A (BA) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A18). If Byte Enable B (BB) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A18). Likewise, BC and BD correspond with the IO pins IO16 to IO23 and IO24 to IO31, respectively. To read from the device, take Chip Enables (CE1, CE2, and CE3 LOW), and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If the first Byte Enable (BA) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte Enable B (BB) is LOW, then data from memory appears on IO8 to IO15. Likewise, Bc and BD correspond to the third and fourth bytes. For more information, see Truth Table on page 9 for a complete description of read and write modes. The input and output pins (IO0 through IO31) are placed in a high impedance state when the device is deselected (CE1, CE2, or CE3 HIGH), the outputs are disabled (OE HIGH), the byte selects are disabled (BA-D HIGH), or during a write operation (CE1, CE2 and CE3 LOW, and WE LOW). High speed tAA = 10 ns Low active power ICC = 175 mA at 10 ns Low CMOS standby power ISB2 = 25 mA Operating voltages of 3.3 0.3V 2.0V data retention Automatic power down when deselected TTL compatible inputs and outputs Easy memory expansion with CE1, CE2, and CE3 features Available in Pb-free 119-Ball PBGA package Logic Block Diagram WE CE1 CE2 CE3 OE BA BB BC BD CONTROL LOGIC INPUT BUFFERS A(9:0) 512K x 32 ARRAY OUTPUT BUFFERS ROW DECODER SENSE AMPS IO0 - IO31 COLUMN DECODER A(18:10) Cypress Semiconductor Corporation Document Number: 38-05477 Rev.*D * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised September 06, 2007 CY7C1062DV33 Selection Guide -10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 175 25 Unit ns mA mA Pin Configuration Figure 1. 119-Ball PBGA (Top View) [1] 1 A B C D E F G H J K L M N P R T U IO16 IO17 IO18 IO19 IO20 IO21 IO22 IO23 NC IO24 IO25 IO26 IO27 IO28 IO29 IO30 IO31 2 A A Bc VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A 3 A A CE2 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Bd A A 4 A CE1 NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE 5 A A CE3 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Bb A A 6 A A Ba VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A 7 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 NC IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 Note 1. NC pins are not connected on the die. Document Number: 38-05477 Rev.*D Page 2 of 11 CY7C1062DV33 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VCC Relative to GND [2] ....-0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State [2]................................... -0.5V to VCC + 0.5V DC Input Voltage [2] ............................... -0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............. ...............................>2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Operating Range Range Industrial Ambient Temperature -40C to +85C VCC 3.3V 0.3V DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage [2] Test Conditions [3] VCC = Min, IOH = -4.0 mA VCC = Min, IOL = 8.0 mA -10 Min 2.4 0.4 2.0 -0.3 VCC + 0.3 0.8 +1 +1 175 30 25 Max Unit V V V V A A mA mA mA Input Leakage Current Output Leakage Current GND < VI < VCC GND < VOUT < VCC, Output disabled -1 -1 VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC IOUT = 0 mA CMOS levels Automatic CE Power Down Current -- TTL Inputs Automatic CE Power Down Current --CMOS Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Note 2. VIL (min) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 , CE2 and CE3 LOW. When HIGH, CE indicates the CE1, CE2, or CE3 HIGH. Document Number: 38-05477 Rev.*D Page 3 of 11 CY7C1062DV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance IO Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max 8 10 Unit pF pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still air, soldered on a 3 x 4.5 inch, four layer printed circuit board 119-Ball PBGA 20.31 8.35 Unit C/W C/W AC Test Loads and Waveforms The AC test loads and waveform diagram follows. [4] OUTPUT Z0 = 50 50 30 pF* VTH = 1.5V 3.3V OUTPUT 5 pF* *Including jig and scope R1 317 R2 351 (b) (a) *Capacitive Load consists of all components of the test environment 3.0V GND All input pulses 90% 10% (c) 90% 10% Rise Time > 1V/ns Fall Time:> 1V/ns Note 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document Number: 38-05477 Rev.*D Page 4 of 11 CY7C1062DV33 AC Switching Characteristics Over the Operating Range [5] Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Cycle[9, 10] Write Cycle Time CE Active LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z [7] WE LOW to High Z [7] [3] Description -10 Min 100 10 10 3 10 5 1 5 3 5 0 Max Unit VCC (Typical) to the First Access [6] Read Cycle Time Address to Data Valid Data Hold from Address Change CE Active LOW to Data Valid [3] OE LOW to Data Valid OE LOW to Low Z [7] [7] s ns ns ns ns ns ns ns ns ns ns 10 5 ns ns ns 5 ns ns ns ns ns ns ns ns ns ns 5 ns ns OE HIGH to High Z CE Active LOW to Low Z [3, 7] CE Deselect HIGH to High Z CE Active LOW to Power Up Byte Enable to Data Valid Byte Enable to Low Z [7] [7] [3, 7] [3, 8] [3, 8] CE Deselect HIGH to Power Down 1 Byte Disable to High Z 10 7 7 0 0 7 5.5 0 3 7 Byte Enable to End of Write Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads and Waveforms, unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 7. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured 200 mV from steady state voltage. 8. These parameters are guaranteed by design and are not tested. 9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 LOW, CE3 LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No.2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05477 Rev.*D Page 5 of 11 CY7C1062DV33 Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR [11] tR [12] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 2V, CE > VCC - 0.2V, VIN > VCC - 0.2V, or VIN < 0.2V 0 tRC Conditions [3] Min 2 25 Typ Max Unit V mA ns ns Data Retention Waveform DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR Switching Waveforms Figure 2. Read Cycle No. 1 [13, 14] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Notes 11. Tested initially and after any design or process changes that affects these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s 13. Device is continuously selected. OE, CE, BA, BB, BC, BD = VIL. 14. WE is HIGH for read cycle. Document Number: 38-05477 Rev.*D Page 6 of 11 CY7C1062DV33 Switching Waveforms (continued) Figure 3. Read Cycle No. 2 (OE Controlled) [3, 14, 15] ADDRESS tRC CE tACE OE tDOE tLZOE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% DATA VALID tPD 50% tHZCE tHZBE tHZOE BA, BB, BC , BD HIGH IMPEDANCE ICC ISB Figure 4. Write Cycle No. 1 (CE Controlled) [3, 15, 16, 17] tWC ADDRESS CE tSA tSCE tAW tPWE WE t BW BA, BB, BC , BD tSD DATA IO tHD tHA Notes 15. Address valid before or similar to CE transition LOW. 16. Data IO is high impedance if OE or BA, BB, BC, BD = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05477 Rev.*D Page 7 of 11 CY7C1062DV33 Switching Waveforms (continued) Figure 5. Write Cycle No. 2 (WE Controlled, OE LOW) [3, 15, 16, 17] tWC ADDRESS tSCE CE tAW tSA WE tBW BA, BB, BC , BD tHZWE DATA IO tLZWE tPWE tHA tSD tHD Figure 6. Write Cycle No. 3 (BA, BB, BC, BD Controlled) [3] tWC ADDRESS tSA BA, BB, BC , BD tAW tBW tHA tPWE WE tSCE CE tSD DATA IO tHD Document Number: 38-05477 Rev.*D Page 8 of 11 CY7C1062DV33 Truth Table CE1 H X X L L L L L L L L L L L CE2 X H X L L L L L L L L L L L CE3 X X H L L L L L L L L L L L OE X X X L L L L L X X X X X H WE X X X H H H H H L L L L L H BA X X X L L H H H L L H H H X BB X X X L H L H H L H L H H X Bc X X X L H H L H L H H L H X BD X X X L H H H L L H H H L X IO0-IO7 High Z High Z High Z Data Out Data Out High Z High Z High Z Data In Data In High Z High Z High Z High Z IO8-IO15 IO16-IO23 IO24-IO31 High Z High Z High Z Data Out High Z Data Out High Z High Z Data In High Z Data In High Z High Z High Z High Z High Z High Z Data Out High Z High Z Data Out High Z Data In High Z High Z Data In High Z High Z High Z High Z High Z Mode Power Down Power Down Power Down Read Byte A Bits Only Read Byte B Bits Only Read Byte C Bits Only Power (ISB) (ISB) (ISB) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) (ICC) Data Out Read All Bits High Z High Z High Z Data Out Read Byte D Bits Only Data In High Z High Z High Z Data In High Z Write All Bits Write Byte A Bits Only Write Byte B Bits Only Write Byte C Bits Only Write Byte D Bits Only Selected, Outputs Disabled Selected, Outputs Disabled L L L X X H H H H High Z High Z High Z High Z (ICC) Document Number: 38-05477 Rev.*D Page 9 of 11 CY7C1062DV33 Ordering Information Speed (ns) 10 Ordering Code CY7C1062DV33-10BGXI Package Diagram Package Type Operating Range Industrial 51-85115 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Fee) Package Diagram Figure 7. 119-Ball PBGA (14 x 22 x 2.4 mm) 51-85115-*B Document Number: 38-05477 Rev.*D Page 10 of 11 CY7C1062DV33 Document History Document Title: CY7C1062DV33 16-Mbit (512K X 32) Static RAM Document Number: 38-05477 REV. ** *A *B ECN NO. 201560 233748 469420 Issue Date See ECN See ECN See ECN Orig. of Change SWI RKF NXR Advance datasheet for C9 IPP 1.AC, DC parameters are modified as per EROS (Spec # 01-2165) 2.Pb-free offering in the Ordering Information Converted from Advance Information to Preliminary Removed -8 and -12 speed bins from product offering Removed Commercial operating Range Changed J7 Ball of PBGA from DNU to NC in the pinout diagram Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page 2 Changed ICC(Max) from 220 mA to 150 mA Changed ISB1(Max) from 70 mA to 30 mA Changed ISB2(Max) from 40 mA to 25 mA Specified the Overshoot specification in footnote 1 Changed tSD from 5.5 ns to 5 ns Added Data Retention Characteristics table and waveform on page 5. Updated the 48-pin FBGA package Updated the Ordering Information Table Added note 1 for NC pins Updated Test Condition for ICC in DC Electrical Characteristics table Added note for tACE, tLZCE, tHZCE, tPU, tPD, and tSCE in AC Switching Characteristics Table on page 4 Description of Change *C 499604 See ECN NXR *D 1462583 See ECN VKN/AESA Converted from preliminary to final Updated block diagram Changed ICC spec from 150 mA to 175 mA Updated thermal specs (c) Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05477 Rev.*D Revised September 06, 2007 Page 11 of 11 All product and company names mentioned in this document are the trademarks of their respective holders. |
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